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om .c 4U t eENGINEERING SPECIFICATIONS he TFT COLOR LCD MODULE aS t a D TM070WA-22L06 . w *18cm (7 inch) diagonal w *Resolution (480xR*G*Bx234 dots) w
m o .c U t4 e e h S ta a .D w w w
(PRELIMINARY)
July.12.2001 Ver. 1 Tottori SANYO Electric Co., Ltd. Electronic Device Business Headquarters LCD Division
3-201, Minami-yoshikata, Tottori, 680-8634 Japan TEL: 81-857-21-3414 FAX: 81-857-21-3418 Department Manager T.FUJITA Engineering Manager
*With CFL backlight unit *Nonglare surface type
om .c 4U et he K.AOKI aS at .D w w w
n REVISION HISTORY
DATE July.12,'01 REVISION NO. Ver.1 PAGE Initial release
DESCRIPTIONS
Tottori SANYO Electric Co., Ltd.
TM070WA-22L06
Ver.1
Page
n NOTICES
1. Please carefully treat this spec since it includes the copyright-related contents. It is strictly prohibited to copy or reprint this spec regardless of partially or whole, without our prior written approval. 2. Content in this spec shall not guarantee any of the third party's intellectual property right or other patents. Tottori SANYO will not be liable for the industrial property issue arising between user and the third party. 3.This product is designed and manufactured only for general AV instruments usage. It is not suitable for the purpose or equipment that required extremely high reliability or safety. Ex: Aerospace instrument, control equipment for nuclear power, live support devices, etc. 4.Please use this product correctly according to operating conditions and precautions for use stated in this document. Please install safety proof in your designing to avoid human accident, fire accident and social damage which may be resulted from malfunction of this product.
5.Radiation proof design is not applied on this product. 6.Tottori SANYO will not be liable for any damages or disadvantages caused by our product in the event that user does not follow condition or precaution stated in our spec.
7.Separate inspection standard spec is applied for cosmetic criteria.
8.If you should have questions on this product, please kindly contact our sales section.
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n MECHANICAL CHARACTERISTICS
ITEM Module size Resolution Dot pitch Pixel pitch Active viewing area Bezel opening area Weight SPECIFICATION 167.0(W)x102.0(H)x11.0typ(t) 480xR*G*B(W)x234(H) 0.107(W)x0.372(H) 0.321(W)x0.372(H) 154.1(W)x87.05(H) 158.1(W)x91.0(H) 220 TYP.
Ta=25deg. UNIT mm pixel mm mm mm mm g
n ABSOLUTE MAXIMUM RATINGS
ITEM Logic/Source power supply voltage Power supply voltage for gate driver Common electrode driving signal TFT exclusive RGB Input signals Output signals Lamp current Ambient temperature Humidity SYMBOL VSH H H-L L CONDITIONS MIN -0.3 MAX 6.0 UNIT NOTE Common power supply V
voltage of Logic
VGH VGH-VGL VGL VCOM DC P-P VR,VB,VG VI VO Ll TST Storage TOP Operation TaC=<60deg. -
-0.3 28 0 33 -16.0 +0.3 0 3.0 0 6.0 -0.3 VSH+0.3 -0.3 VSH+0.3 -0.3 VSH+0.3 3 4.5 85 -30 85 -30 90
V V V V V V V V mA deg. %RH
Note 1),2) not beyond 240H Note 3)
Note 1) Care should be taken so that the LCD module may not be subjected to the temperature beyond this specification. Note 2) Ambient temperature shows temperature on LCD surface. Module temperature is apt to increace while it's driving due to CFL heat etc. Please design carefully not to exceed +85 degree C on every surface of LCD that shoud come to contact with any other equipment. Temperature for operation is one which only assures LCD operation. Contrast, response time,or other LCD quality is regulated under condition of Ta=+25 degree C. Note 3) Please be advised that dew condensation level should be less than maximum wet bulb temperature 58 degree C. Dew condensation may induce leak current, and also influence LCD performance.
n MECHANICAL ENVIRONMENT
Vibration Shock
-
Storage Storage
-
2.9 100
G G
Note 1)
XYZ 6ms/direction
Note 1) Vibration frequency : 8 - 33.3 Hz displacement : 1.3mm Vibration frequency : 33.3 - 400Hz Sweep time : 15 min./1 sweep total test time : X,Y-2Hr Z-4Hr
Z
X
Y
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n OPTICAL CHARACTERISTICS (1)
Ta=25deg., VSH=5.3V, fV=60Hz ITEM Viewing angle range Contrast ratio Response Rise time Fall Color of CIE White Coordinate
SYMBOL
CONDITIONS
= 0 deg.
MIN
TYP
MAX
UNIT
NOTE
Note 1),4)
K=>5
= 90 deg. =180 deg. =270 deg.
K tr tf x y
=0 deg., =0 deg. =0 deg., =0 deg. =0 deg., =0 deg.
100
-
30 20 0.300 0.298
40 60 30 60 -
deg.
ms.
Note 2),4) Note 3),4)
Note 4)
=180 deg.
DATA
Black
White
Black
100% =90 deg. =270 deg. 0% =0 deg. Tr Tf B 90%
10%
Note 1) and are defined as above figure.
Note 3) Response time
Note 2) Contrast ratio "K" is defined below formula. K= Brightness at ON (White) Brightness at OFF (Black)
Note 4) Measurement codition j VSH=5.3V,VGH=15V,VGL=-14.0V,VCOM DC=1.8V,VCOM P-P=5.0V k VR/VG/VB DC=VSH/2, VR/VG/VB AC=4.0V l Follow brightness measurement condition in next item.
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n OPTICAL CHARACTERISTICS (2)
Ta=25 deg. ITEM Brightness SYM. CONDITIONS MIN B TYP MAX 400 UNIT cd/m
2
NOTE Surface Brightness of LCD
Note) The brightness shall be the following point. 1/2Hp Active area
1/2Vp
Fig.1 Measurement point
Vp :Total Number of Vertical pixel Hp :Total Number of horizontal pixel
Measurement equipment : BM-7(TOPCON Corp.) Measurement condition j Ambient temperature : 25 2 deg. k LCD : All pixels are WHITE l Measure after 30 minutes of CFL warm up. m IL=4.5mArms, CFL inverter: Operating TDK CXA-L0612A-VJL or equivalent inverter with capability of frequency 50kHz, Lamp current max.4.5mA
n BACKLIGHT CHARACTERISTICS
Ta=25 deg. ITEM Lamp voltage Lamp current Operating frequency Start up voltage Start up voltage Lamp life Backlight power supply SYM. CONDITIONS MIN VL IL fL VS1 VS2 tOL WL 3.0 40 10000 TYP MAX 740 48 3.3 4.5 55 1750 1800 UNIT NOTE Vrms at IL=4.5mArms mArms (Recommended value) KHz (Recommended value) Vrms at Ta= 25 deg. Vrms at Ta=-30 deg. Hours at IL=4.5mArms, Note 1) W at IL=4.5mArms
Note 1) CFL Lamp life indicates time from initial Lamp brightness to half of original brightness. Note 2) Inverter GND shall be connected to LCD frame.(Please refer to outer dimension drawing) LCD frame is connected to internal circuitry GND.
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n BLOCK DIAGRAM
Tottori SANYO Electric co., Ltd. TM070WA-22L06 Ver.1 Page 5/20
IF BLOCK 24PIN SIGNAL HSYIO VSYIO CKH CSY N/P L/R U/D SWC DM1 DM2 DM3 POLC POLV PWM TEST SWV
480x(RGB)x234
Timing Contoller
TFT Panel
vco
TFT exclusive RGB
FPC
VR VG VB VSH VCOM VGH VGL GND
Power supply voltage Level Shift
n INTERFACE PIN CONNECTIONS
LCM : CN PIN NO. SYMBOL 1 HSYIO 2 POLC 3 CSY 4 VGH 5 POLV 6 VB 7 VR 8 VG 9 GND 10 VSH 11 VGL 12 VCOM 13 N/P 14 VSYIO 15 L/R 16 U/D 17 SWC 18 PWM 19 TEST 20 CKH 21 DM1 22 DM2 23 DM3 24 SWV I/O I/O O I I O I I I I I I I I I/O I I I O O I/O I I I O FUNCTION Input/Output horizontal sync.signal(low active) Polarity alternating signal for common signal Composite sync.signal(high active) Power supply for gate driver(high level) Polarity alternating signal for video signal) Color video signal(Blue) Color video signal(Red) Color video signal(Green) GND Positive power supply voltage Power supply for gate driver(low level) Common electrode driving signal Selection for NTSC or PAL(NTSC=VSH,PAL=GND) Input/Output vertical sync.signal(low active) Selection for horizontal scanning direction Selection for vertical scanning direction Selection for input/output direction of CKH,HSYNC,VSYNC Timinng signal for PWM dimming of backlight Open use only Input/output clock signal Selection for display mode Selection for display mode Selection for display mode Video selection timming signal
I/F CN : SFR24R-1ST(FCI) Suitable FPC : Pitch 0.8mm,Width 20mm
Back Light : FLCN PIN NO. SYMBOL FUNCTION 1 H.V High voltage for CFL 2 N.C No Connection 3 LGND Low voltage for CFL FLCN : BHR-03VS-1(JST) Suitable mating connector : SM02(8.0)B-BHS-1(JST)
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n RELATIONSHIP BETWEEN INPUT DATA AND DISPLAY POSITION
1*1 2*1 3*1 1*2 2*2 1*3 ************ 1*479 1*480 2*480 *
* * * * 233*1 234*1 234*2
Vp * Hp
RGB
* * * *
233*480 234*480
* * * * * * * * * * * * * * * 234*479
n FUNCTION,MODE AND TERMINALS
Mode terminals SWC N/P DM1 DM2 DM3 H H L H L or L L H L L L L H H H L H or L H H other settings or H or L L L H H H H Sync. signal I/O terminals CSY HSYIO VSYIO CKH SWV Hsync Vsync Lo Test Conposite output output output signal sync input output Hsync Vsync Lo masking Conposite output output output signal sync input output Hsync Vsync Lo Lo Conposite output output output output sync input Hsync input Vsync input Pixel clock input Lo output Remarks Test mode NTSC or PAL mode (Normal mode) NTSC or PAL mode
(Full,Wide,Cinema)
Input Hi or External clock Lo fixed synchronous mode value
Note 1) We recommend external clock synchronize method except for TV display usage. Note 2) Please invert polarity of video signal VR,VG and VB in sync with invert timing of POLV signal.(Please refer Figure A.) Note 3) Please invert polarity of VCOM in sync with invert timing of POLC signal. (Please refer Figure B.) Note 4) Horizontal synchronized signal is output in sync with CSY signal when SWC is Hi. When SWC is Low, LCD module is operated in sync with Horizontal synchronized signal for HSYIO terminal.(Please refer Figure C,D,G and F.) Note 5) In normal mode, non-display area at both edge of display can be better screened by masking video signal following SWV output signal. (Please refer timing chart E.) Note 6) PWM signal for CFL brigtness control is output form PWM terminal. (Please refer Figure H.) But please use it when normal NTSC or PAL signals are inputted.
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n DISPLAY METHOD AND CHARACTERISTICS
Horizontal Vertical
Disply area SOURCE Disply area Signal area Signal area Same Senter :Slow Botn side:Fast 4:3 signal Signal area & Blank Wide signal(16:9) Signal area 4:3 signal Signal area Senter :Slow Botn side:Fast
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H=VSH L=GND
DM1 DM2 DM3 H H H H H L Display Mode Display method, Feature Display 4:3 image long sideways. Display perfect circle around center better than Full screen mode. H L H Sampling Senter Both side
NTSC S=1/1 S=1/1
PAL
S=6/7
Compress
Full mode Wide1 mode
4:3 signal
Navigation Signal 4:3 signal
EXAMPLE Fig.2-1 Fig.2-2
S=6/7
Compress
Normal mode
Display perfect circle all around the screen. Both edge screen can be masked with SWV.
S=1/1
S=6/7
Compress
Fig.2-3
H L
L H
L H
Cinema mode Display 16:9 image. Wide 2 mode
Display perfect circle around center better than Wide 1 mode. Top and bottom images are eliminated.
Senter Both side Same Senter :Slow Botn side:Fast
S=4/3 Extend S=5/4 Extend -
S=20/21
Compress
Fig.2-4 Fig.2-5
S=10/11
Compress
L L L
H L L
L H L
Test mode Test mode Test mode
This mode is unusable due to test mode. This mode is unusable due to test mode. This mode is unusable due to test mode.
-
-
-
-
-
Fig2-1 Full mode
Fig2-2 Wide1 mode
Fig2-3 Normal mode
Fig2-4 Chinema mode
Fig2-5 Wide 2 mode
jNTSC MODE(N/P=H, SWC=H) (a1)Horizontal...Full mode, Wide1 mode, Wide2 mode, Cinema mode From falling edge of HSYIO output to 12.8-63.1S. (a2)Horizontal...Normal mode From falling edge of HSYIO output to 7.5-68.5S. (b1)Vertical...Full mode, Wide2 mode, Normal mode From falling edge of VSYIO output to 20H-253H. (b2)Vertical...Cinema mode From falling edge of VSYIO output to 49H-224H. (b3)Vertical...Wide2 mode From falling edge of VSYIO output to 42H-228H. kPAL MODE(N/P=L, SWC=L) (a1)Horizontal...Full mode, Wide1 mode, Wide2 mode, Cinema mode From falling edge of HSYIO output to 12.8-63.1S. (a2)Horizontal...Normal mode From falling edge of HSYIO output to 7.5-68.5S. (b1)Vertical...Full mode, Wide2 mode, Normal mode From falling edge of VSYIO output to 26H-298H. Except for Even Nunber Field (14n+12) and (14n+20), Odd Number Field (14n+17) and (14n+23). n=(1,2,3,...,20) (b2)Vertical...Cinema mode From falling edge of VSYIO output to 40H-284H. Except for Even Nunber Field (42n+13) and (14n+35), Odd Number Field (42n) and (42n+22). n=(1,2,3,...,6) (b3)Vertical...Wide2 mode From falling edge of VSYIO output to 35H-289H. Except for Even Nunber Field (22n+14) and (22n+24), Odd Number Field (22n+21) and (22n+31). n=(1,2,3,...,12) lEXTERNAL CLOCK MODE(N/P=H, SWC=L,DM1,2,3=H) (a1)Horizontal From falling edge of HSYIO output to 99-578CLK. CLK is indicated as external CLK number. (b3)Vertical From falling edge of VSYIO output to 20H-253H.
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n ELECTRICAL CHARACTERISTICS
VSH=5.3V, Ta=25 deg.
ITEM SYMBOL CONDITIONS MIN TYP Logic/Source VSH 5.0 5.3 power supply voltage VGH Power supply voltage H 14.5 15.0 VGL for gate driver L -14.5 -14.0 Common electrode driving DC center 1.0 1.8 VCOM signal P-P 4.0 5.0 TFT exclusive RGB DC center TYP-0.1 VSH/2 VR,VG,VB AC White pattern +1.5 2.0 AC Black pattern -1.5 -2.0 AC White pattern -1.5 -2.0 AC Black pattern +1.5 2.0 VIH High level 0.7VSH Input signals VIL Low level 0 Input signals VIH High level 0.8VSH VIL Low level 0 Output signals VOH High level VSH-2.1 VOL Low level 50 Power Supply current IVSH VSH=5.3V 1.2 IVGH VGH=15V IVGL VGL=-14.0V 6 WS Power Supply 367
MAX 5.5 15.5 -13.5 2.5 6.0 TYP+0.1 VSH/2 -VSH/2 -VSH/2 VSH/2 VSH 0.3VSH VSH 0.2VSH 0.4 80 3 15 679
UNIT V V V V V V V V V V V V V V V V mA mA mA mW
NOTE
Note 3)
Note 1) Note 2),4) Note 3)
POLV=H Note4),5) POLV=H Note4),5) POLV=L Note4),5) POLV=L Note4),5)
Note 6) Note 7) Note 8) Note 9,10)
Note 1)
Please adjust DC voltage on opposite electrode (VCOM) to optimum BIAS voltage in order to minimize
flicker.
Note 2) Note 3) Note 4) Note 5) Note 6) Note 7) Please optimize voltage of each module to achieve optimum contrast. Please control voltage fluctuation less than 0.1V after VCOM is adjusted. =+/- amplitude shall be symmetry. In case of POLV=Low, the signal polarity inverts working with polarity of VCOM. Symmetric terminal name: HSYIO,VSYIO(CMOS INPUT) Symmetric terminal name: CSY,N/P,L/R,U/D,SWC,CKH,DM1,DM2,DM3( CMOS Schmitt INPUT)
Note 8) Symmetric terminal name: HSYIO,POLC,POLV,VSYIOUnder the following conditions:
Display pattern: ALL BLACK FULL MODE fv:60Hz
VCOM DC=1.8V,VCOM P-P=5.0V VR/VG/VB DC=VSH/2 VR/VG/VB AC=4.0V
Note10) Value for module circuitry portion (except for backlight)
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n ELECTRICAL CHARACTERISTICS AC TIMING
NTSC :fH=15.73kHz,fV=60Hz,t HI=4.7s PAL :fH=15.63kHz,fV=50Hz,t HI=4.7s (SWC=Hi or Low)
VSH=5.3V GND=0V, Ta=25 deg.
ITEM Input voltage
Input composite sync rising time [CSY]Vertical location falling time Polarity alternating delay time [POLV-VRGB] Polarity alternating delay time[POLC-VCOM]
Output polarty signal [POLC,POLV]
rising time falling time
SYMBOL VID t rVI t fVI t DV t DC t rPL t fPL
MIN 0
-
TYP -
-
-
MAX VSH 0.2 0.2 4 4 0.5 0.5
UNIT V s s s s s s
NOTE

(SWC=Hi )
VSH=5.3V GND=0V, Ta=25 deg.
ITEM SYMBOL fH(N) Input composite sync frequency NTSC fH(P) horizntal location PAL t HI(N) pulse wide NTSC t HI(P) PAL t rHI1 rising time t fHI1 [CSY] falling time fV(N) Input composite sync frequency NTSC fV(P) Vertical location PAL t VI(N) pulse wide NTSC t VI(P) [CSY] PAL fH0 Output horizontal frequency t H0 sync signal pulse wide t rH0 rising time t fH0 [HSYIO] falling time horizontal sync phase t pd1 rising HSY t pd2 [HSYIO-CSY] falling HSY fV0 Output vertical frequency t V0 sync signal pulse wide t VH0 Output phase t rV0 [VSYIO] rising time t fV0 falling time t DV1 Vertical sync phase ODD FIELD t DV2 [CSY-VSYIO] EVEN FIELD
MIN TYP MAX 15.13 15.73 16.33 15.03 15.63 16.23 4.2 4.7 5.2 4.2 4.7 5.2 0.5 0.5 fH/284 fH/262.5 fH/258 fH/344 fH/312.5 fH/304 3 2.5 fH 4.7 0.5 0.5 2.1 2.1 fV 4 11 0.5 0.5 1 0.5 -
UNIT kHz kHz s s s s Hz Hz H H kHz s s s Hz Hz Hz H s s s H H
NOTE
Note 1
Note 1
Note 2
1H=1/fH Sync HSYIO
Note 1) Note 2)
Standard complex synchronized signal [CSY] type of NTSC/PAL signal shall be inputted. It would be a factor of display quality degradation if nonstandard synchronized signal were inputted. Varied by tpd1 value.
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(SWC=Low )
VSH=5.3V GND=0V, Ta=25 deg.
ITEM Input CLK sync signal frequency H pulse wide L pulse wide rising time [CKH] Input horizontal sync signal [HSYIO] Input Vertical sync signal [VSYIO] Data setup time Data hold time Data setup time Data hold time falling time frequency pulse wide rising time falling time frequency pulse wide
SYMBOL fCL1 t WH t WL t rCL1 t fCL1 fHI t HI t rHI2 t fHI2 fVI t VI t SU1 t HO1 t SU2 t HO2
MIN 8.5 20.0 20.0 1 50 1 25 25 1.0 1.0
TYP 9.5 5 3 -
MAX 9.8 10.0 10.0 9 0.05 0.05 5 -
UNIT MHz ns ns ns ns kHz s s s Hz H ns ns s s
NOTE
fCLI/650 fCLI/608 fCLI/590
fHI/262 fHI/258
Note 3)
Note 4)
Note 3)
In external clock input mode, they show input phase contrast of CKH and HSYIO signal. Data is loaded latching with CKH rising signal.
Note 4)
In external clock input mode, they show input phase contrast of HSYIO andVSYIO signal. Data is loaded latching with HSYIO falling signal.
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n ELECTRICAL CHARACTERISTICS AC TIMING
(SWC=Hi or Low)
t rPL
t fPL
POLV
t DV
WHITE
BLACK
VR AC VG DC(center) VB AC
+2V(TYP.) -2V(TYP.) BLACK WHITE
VSH/2
Fig-A
t rPL t fPL
POLC
t DC
VCOM DC(center)
(1.8V)
+2.5V(TYP.) P-P -2.5V(TYP.)
Fig-B

(SWC=Hi NTSC/PAL)
t rHI1
t fHI1
CSY
t pd1
t HI t pd2
1H=63.5s(NTSC) 1H=64.0s(PAL)
HSYIO
t fHO t HO
t rHO
Fig-C
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t VI
CSY
ODD FIELD t VO EVEN FIELD t DV2
t DV1
VSYIO
t rVI t fVI t rVO t fVO
VSYIO
t VHO t VHO
HSYIO
HSYIO
1H=63.5S(NTSC) 1H=64.0S(PAL)
POLV
Fig-D
HSYIO
13.1s 50.1s
SWV
MASKING PERIOD
IMAGE PERIOD
MASKING PERIOD
Fig-E (NORMAL MODE DM1=Hi, DM2=Low, DM3=Hi)
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(SWC=Low)
t VI
VSYIO
t rVI
t fVI
VSYIO HSYIO
t HI
t HO2
t SU2
t fHI2
t rHI2
HSYIO
1H=63.5S(typ.)
POLV Fig-F (N/P=Hi)
CKH
t HO1 t SU1
t fCL1
t rCL1 t WL t WH
HSYIO
t HI
t fHI2
t rHI2
POLV
t DV
WHITE
BLACK
VR VG DC(center) VB
BLACK WHITE
Fig-G(N/P=Hi, DM1=DM2=DM3=Hi)
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n PWM DIMMING TIMING
VSYIO 525H(NTSC) 625H(PAL)
PWM 105H
(NTSC)
Tottori SANYO Electric Co., Ltd.
89H 525H(NTSC) 625H(PAL) magnify time
nH 1H 105H(NTSC) 89H(PAL) nH Inverter oscillation Inverter no oscillation
PWM (PAL)
VSYIO
TM070WA-22L06
HSYIO
PWM
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Fig-H
n POWER ON/OFF SEQUENCE REQUIREMENT
VGH
VSH VGH,VSH VGL
VGL
MIN 2V
MIN 2V
SIGNALS
MIN 1V
MIN 1V
CFL
* (V=1 FIELD time)
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n PRECAUTIONS
Caution for designing 1. This technical spec just explains general specification of the LCD module. Please request us customer specification before you start designing. 2. Please apply waterproof design to avoid any moisture or saline matter into LCD module.
3. Long CFL wiring may result in increase of leak current. Please carefully design the wiring in order to minimize leak current, which causes reduction of inverter start-up voltage. 4. Please implement enough shielding for LCD's excess nose radiation not to interfere other peripheral device by. Caution for LCD handling 1. Disassembling or remodeling of LCD module is prohibited. 2. Please do not touch volume control no the backside of module. In the case you change it, LCD module may not achieve proper performance mentioned in the spec. 3. LCD shall be stored in same packing material during import, and under the condition of room temperature (10-30 degree C). Please do not leave LCD modules under the direct sunlight or strong infra-red radiation for a long period time to prevent liquid
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4. LCD module integrates semi-conductor components. Please handle it with static electricity protection. 5. Please turn off the power supply before plugging or unplugging LCD module. 6. Since high voltage is supplied to CFL when it's driving, please make careful treatment and design around CFL portion. And please be sure that CFL connector does not have a loose connection to prevent large risk of fire due to high voltage. 7. Please do not rub, push, or hit LCD surface with hard tool etc. Film on surface is easily scratched. When droplets of water or dirt are on the surface, please gently remove them with soft fabric. 8. Glass in LCD module is easily damaged or broken when it is dropped, strongly pinched or hit. Please be careful not to cut your hand if you break the glass. 9. In case that liquid crystal fluid runs off from broken panel, please do not swallow or handle the fluid for any reason. If liquid crystal accretes hands or clothes, please remove it with or alcohol and wash them. By any chance, liquid crystal ge. 10.Cold Cathode Lamp contains small amount of mercury. Please follow local ordinances or regulation for disposal.
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